As high data rate interfaces such as Universal Serial Bus (USB) 3.0, High-Definition Multimedia Interface (HDMI) or Thunderbolt make their way to a huge number of applications, the need for a highly effective electrostatic discharge (ESD) protection device is growing. The intrinsic ESD device resistance needs to be very low in order to properly discharge critical ESD incidents. The silicon (Si) substrate is a main contributor to the intrinsic resistance (e.g. makes up to 70%) of the ESD device. The ESD device may include one or more diodes, and thus, the performance of these diodes may improve with thinner silicon. When lowering the silicon thickness down to below 35 μm, a variety of new processing issues may occur. The mechanical stability of the chip may decrease to an extent that traditional preassembly and packaging processes (e.g. dicing, die pick) may result in unwanted chip damage like chipping or chip cracks.
As the current flow in an ESD device may be through the silicon (vertical current direction), the wafer backside may be provided with a metal contact. This metal layer may be deposited on the wafer backside acting as a solder layer. This may be to achieve a good electrical contact of the silicon to the lead frame and to mechanically attach the chip to the lead frame. Conventionally, the metal layer may be sputtered on the wafer and the metal layer may be separated at the same time as the silicon using a mechanical wafer dicing process, e.g. sawing. Sawing silicon and metal at the same time may be critical due to metal sticking on the sawing blade. Dicing defects may occur as the blade may change its properties due to blocking of the diamond grains of the dicing blade. The process window for excellent dicing performance may be limited by the ratio of silicon thickness (higher is better) and metal thickness (lower is better). Thus lowering the silicon thickness may cause an increase in dicing issues.
Further, in a typical die pick process, there may be a needle which lifts the chip from below a dicing foil to reduce the adhesion force (of the dicing foil to the wafer backside), and at the same time there may be a vacuum handler gripping the chip from the front side, transporting the chip to a lead frame. Ultra thin chips may tend to break because the little piece of silicon may not be able to withstand the mechanical force of foil detaching and the force from the push needle from down below. This may be critical especially for very small chip size.
Today, the chip thickness may be limited by manufacturability or manufacturing processes as described above, where for the resulting products, this means that there may be a hard limit on their performance.